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The W5100S chip designed with Hardwared TCP/IP, WIZnet technology, is an embedded Ethernet Controller that enables easier Internet Connection for embedded Systems using SPI (Serial Peripheral Interface) and Parallel System BUS. W5100S suits users in need of stable Internet connectivity best, using a single chip to implement TCP/IP Stack, 10/100 Ethernet MAC and PHY. Hardwired TCP/IP stack supports TCP, UDP, IPv4, ICMP, ARP, IGMP, and PPPoE, …, which has been proven through various Applications over many years. W5100S uses a 16 Kbytes Internal Buffer as its Data Communication Memory. By using W5100S, users can implement the Ethernet Application they need by using a simple Socket Program instead of handling a complex Ethernet Controller. It is possible to use 4 Independent Hardware Sockets simultaneously. SPI (Serial Peripheral Interface) and Parallel System BUS is provided for easy integration with the external MCU. The W5100S SPI supports 70 MHz speed. And also Parallel System Bus supports high speed Network Communication. In order to reduce Power Consumption of the System, W5100S provides WOL (Wake on LAN) and a Power Down Mode.
Not yet . But W5100S is compatible with W5100. Refer to W5100 firmware