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core:mii

MII - the Media Independent Interface (10/100 Mbps)

The MII is a 4 bit parallel interface between level one (PHY) and level two (MAC).
We offer that interface with our chips W3150A+ and W5300 to support external PHY and Switch Chips.
As this two times 4 bit parallel data signals are clock synchronous to RXC (receive clock) and TXC (transmit clock) there are some important points to remember:

  • TXC must be provided by the PHY/Switch chip (maybe need to be activated)
  • The MII clock is 25MHz in the full 4 bit mode (4 + 4 signals)
  • In the “reduced” 2 bit = RMII mode the clock is 50MHz
    • take more care in PCB design
    • less signals (only 2 + 2 signals)
  • all signals must be well shaped without spices and glitches (add 33ohm in series can help)
  • when using a Switch, this Switch chip's MII must be configured as Slave = “Reverse MII”.
    The W3150A+/W5300 provide the MAC ⇒ is Master.
  • RMII is “reduced” not “Reverse MII” - mark that !

external Link Wikipedia

Schematics

WIZnet Chip plus PHY (MII)

WIZnet Chip plus PHY (RMII)

WIZnet Chip plus Switch (Reverse MII)

core/mii.txt · Last modified: 2015/03/16 10:33 (external edit)